00001 // Copyright (C) 2008 Ubixum, Inc. 00002 // 00003 // This library is free software; you can redistribute it and/or 00004 // modify it under the terms of the GNU Lesser General Public 00005 // License as published by the Free Software Foundation; either 00006 // version 2.1 of the License, or (at your option) any later version. 00007 // 00008 // This library is distributed in the hope that it will be useful, 00009 // but WITHOUT ANY WARRANTY; without even the implied warranty of 00010 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00011 // Lesser General Public License for more details. 00012 // 00013 // You should have received a copy of the GNU Lesser General Public 00014 // License along with this library; if not, write to the Free Software 00015 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 00016 00034 #ifndef FX2REGS_H 00035 #define FX2REGS_H 00036 00037 #include "fx2types.h" 00038 00039 xdata at 0xE400 volatile BYTE GPIF_WAVE_DATA; 00040 xdata at 0xE480 volatile BYTE RES_WAVEDATA_END; 00041 00042 // General Configuration 00043 00044 xdata at 0xE600 volatile BYTE CPUCS; 00045 xdata at 0xE601 volatile BYTE IFCONFIG; 00046 xdata at 0xE602 volatile BYTE PINFLAGSAB; 00047 xdata at 0xE603 volatile BYTE PINFLAGSCD; 00048 xdata at 0xE604 volatile BYTE FIFORESET; 00049 xdata at 0xE605 volatile BYTE BREAKPT; 00050 xdata at 0xE606 volatile BYTE BPADDRH; 00051 xdata at 0xE607 volatile BYTE BPADDRL; 00052 xdata at 0xE608 volatile BYTE UART230; 00053 xdata at 0xE609 volatile BYTE FIFOPINPOLAR; 00054 xdata at 0xE60A volatile BYTE REVID; 00055 xdata at 0xE60B volatile BYTE REVCTL; 00056 00057 // Endpoint Configuration 00058 00059 xdata at 0xE610 volatile BYTE EP1OUTCFG; 00060 xdata at 0xE611 volatile BYTE EP1INCFG; 00061 xdata at 0xE612 volatile BYTE EP2CFG; 00062 xdata at 0xE613 volatile BYTE EP4CFG; 00063 xdata at 0xE614 volatile BYTE EP6CFG; 00064 xdata at 0xE615 volatile BYTE EP8CFG; 00065 xdata at 0xE618 volatile BYTE EP2FIFOCFG; 00066 xdata at 0xE619 volatile BYTE EP4FIFOCFG; 00067 xdata at 0xE61A volatile BYTE EP6FIFOCFG; 00068 xdata at 0xE61B volatile BYTE EP8FIFOCFG; 00069 xdata at 0xE620 volatile BYTE EP2AUTOINLENH; 00070 xdata at 0xE621 volatile BYTE EP2AUTOINLENL; 00071 xdata at 0xE622 volatile BYTE EP4AUTOINLENH; 00072 xdata at 0xE623 volatile BYTE EP4AUTOINLENL; 00073 xdata at 0xE624 volatile BYTE EP6AUTOINLENH; 00074 xdata at 0xE625 volatile BYTE EP6AUTOINLENL; 00075 xdata at 0xE626 volatile BYTE EP8AUTOINLENH; 00076 xdata at 0xE627 volatile BYTE EP8AUTOINLENL; 00077 xdata at 0xE630 volatile BYTE EP2FIFOPFH; 00078 xdata at 0xE631 volatile BYTE EP2FIFOPFL; 00079 xdata at 0xE632 volatile BYTE EP4FIFOPFH; 00080 xdata at 0xE633 volatile BYTE EP4FIFOPFL; 00081 xdata at 0xE634 volatile BYTE EP6FIFOPFH; 00082 xdata at 0xE635 volatile BYTE EP6FIFOPFL; 00083 xdata at 0xE636 volatile BYTE EP8FIFOPFH; 00084 xdata at 0xE637 volatile BYTE EP8FIFOPFL; 00085 xdata at 0xE640 volatile BYTE EP2ISOINPKTS; 00086 xdata at 0xE641 volatile BYTE EP4ISOINPKTS; 00087 xdata at 0xE642 volatile BYTE EP6ISOINPKTS; 00088 xdata at 0xE643 volatile BYTE EP8ISOINPKTS; 00089 xdata at 0xE648 volatile BYTE INPKTEND; 00090 xdata at 0xE649 volatile BYTE OUTPKTEND; 00091 00092 // Interrupts 00093 00094 xdata at 0xE650 volatile BYTE EP2FIFOIE; 00095 xdata at 0xE651 volatile BYTE EP2FIFOIRQ; 00096 xdata at 0xE652 volatile BYTE EP4FIFOIE; 00097 xdata at 0xE653 volatile BYTE EP4FIFOIRQ; 00098 xdata at 0xE654 volatile BYTE EP6FIFOIE; 00099 xdata at 0xE655 volatile BYTE EP6FIFOIRQ; 00100 xdata at 0xE656 volatile BYTE EP8FIFOIE; 00101 xdata at 0xE657 volatile BYTE EP8FIFOIRQ; 00102 xdata at 0xE658 volatile BYTE IBNIE; 00103 xdata at 0xE659 volatile BYTE IBNIRQ; 00104 xdata at 0xE65A volatile BYTE NAKIE; 00105 xdata at 0xE65B volatile BYTE NAKIRQ; 00106 xdata at 0xE65C volatile BYTE USBIE; 00107 xdata at 0xE65D volatile BYTE USBIRQ; 00108 xdata at 0xE65E volatile BYTE EPIE; 00109 xdata at 0xE65F volatile BYTE EPIRQ; 00110 xdata at 0xE660 volatile BYTE GPIFIE; 00111 xdata at 0xE661 volatile BYTE GPIFIRQ; 00112 xdata at 0xE662 volatile BYTE USBERRIE; 00113 xdata at 0xE663 volatile BYTE USBERRIRQ; 00114 xdata at 0xE664 volatile BYTE ERRCNTLIM; 00115 xdata at 0xE665 volatile BYTE CLRERRCNT; 00116 xdata at 0xE666 volatile BYTE INT2IVEC; 00117 xdata at 0xE667 volatile BYTE INT4IVEC; 00118 xdata at 0xE668 volatile BYTE INTSETUP; 00119 00120 // Input/Output 00121 00122 xdata at 0xE670 volatile BYTE PORTACFG; 00123 xdata at 0xE671 volatile BYTE PORTCCFG; 00124 xdata at 0xE672 volatile BYTE PORTECFG; 00125 xdata at 0xE678 volatile BYTE I2CS; 00126 xdata at 0xE679 volatile BYTE I2DAT; 00127 xdata at 0xE67A volatile BYTE I2CTL; 00128 xdata at 0xE67B volatile BYTE XAUTODAT1; 00129 xdata at 0xE67C volatile BYTE XAUTODAT2; 00130 00131 #define EXTAUTODAT1 XAUTODAT1 00132 #define EXTAUTODAT2 XAUTODAT2 00133 00134 // USB Control 00135 00136 xdata at 0xE680 volatile BYTE USBCS; 00137 xdata at 0xE681 volatile BYTE SUSPEND; 00138 xdata at 0xE682 volatile BYTE WAKEUPCS; 00139 xdata at 0xE683 volatile BYTE TOGCTL; 00140 xdata at 0xE684 volatile BYTE USBFRAMEH; 00141 xdata at 0xE685 volatile BYTE USBFRAMEL; 00142 xdata at 0xE686 volatile BYTE MICROFRAME; 00143 xdata at 0xE687 volatile BYTE FNADDR; 00144 00145 // Endpoints 00146 00147 xdata at 0xE68A volatile BYTE EP0BCH; 00148 xdata at 0xE68B volatile BYTE EP0BCL; 00149 xdata at 0xE68D volatile BYTE EP1OUTBC; 00150 xdata at 0xE68F volatile BYTE EP1INBC; 00151 xdata at 0xE690 volatile BYTE EP2BCH; 00152 xdata at 0xE691 volatile BYTE EP2BCL; 00153 xdata at 0xE694 volatile BYTE EP4BCH; 00154 xdata at 0xE695 volatile BYTE EP4BCL; 00155 xdata at 0xE698 volatile BYTE EP6BCH; 00156 xdata at 0xE699 volatile BYTE EP6BCL; 00157 xdata at 0xE69C volatile BYTE EP8BCH; 00158 xdata at 0xE69D volatile BYTE EP8BCL; 00159 xdata at 0xE6A0 volatile BYTE EP0CS; 00160 xdata at 0xE6A1 volatile BYTE EP1OUTCS; 00161 xdata at 0xE6A2 volatile BYTE EP1INCS; 00162 xdata at 0xE6A3 volatile BYTE EP2CS; 00163 xdata at 0xE6A4 volatile BYTE EP4CS; 00164 xdata at 0xE6A5 volatile BYTE EP6CS; 00165 xdata at 0xE6A6 volatile BYTE EP8CS; 00166 xdata at 0xE6A7 volatile BYTE EP2FIFOFLGS; 00167 xdata at 0xE6A8 volatile BYTE EP4FIFOFLGS; 00168 xdata at 0xE6A9 volatile BYTE EP6FIFOFLGS; 00169 xdata at 0xE6AA volatile BYTE EP8FIFOFLGS; 00170 xdata at 0xE6AB volatile BYTE EP2FIFOBCH; 00171 xdata at 0xE6AC volatile BYTE EP2FIFOBCL; 00172 xdata at 0xE6AD volatile BYTE EP4FIFOBCH; 00173 xdata at 0xE6AE volatile BYTE EP4FIFOBCL; 00174 xdata at 0xE6AF volatile BYTE EP6FIFOBCH; 00175 xdata at 0xE6B0 volatile BYTE EP6FIFOBCL; 00176 xdata at 0xE6B1 volatile BYTE EP8FIFOBCH; 00177 xdata at 0xE6B2 volatile BYTE EP8FIFOBCL; 00178 xdata at 0xE6B3 volatile BYTE SUDPTRH; 00179 xdata at 0xE6B4 volatile BYTE SUDPTRL; 00180 xdata at 0xE6B5 volatile BYTE SUDPTRCTL; 00181 xdata at 0xE6B8 volatile BYTE SETUPDAT[8]; 00182 00183 // GPIF 00184 00185 xdata at 0xE6C0 volatile BYTE GPIFWFSELECT; 00186 xdata at 0xE6C1 volatile BYTE GPIFIDLECS; 00187 xdata at 0xE6C2 volatile BYTE GPIFIDLECTL; 00188 xdata at 0xE6C3 volatile BYTE GPIFCTLCFG; 00189 xdata at 0xE6C4 volatile BYTE GPIFADRH; 00190 xdata at 0xE6C5 volatile BYTE GPIFADRL; 00191 00192 xdata at 0xE6CE volatile BYTE GPIFTCB3; 00193 xdata at 0xE6CF volatile BYTE GPIFTCB2; 00194 xdata at 0xE6D0 volatile BYTE GPIFTCB1; 00195 xdata at 0xE6D1 volatile BYTE GPIFTCB0; 00196 00197 xdata at 0xE6D2 volatile BYTE EP2GPIFFLGSEL; 00198 xdata at 0xE6D3 volatile BYTE EP2GPIFPFSTOP; 00199 xdata at 0xE6D4 volatile BYTE EP2GPIFTRIG; 00200 xdata at 0xE6DA volatile BYTE EP4GPIFFLGSEL; 00201 xdata at 0xE6DB volatile BYTE EP4GPIFPFSTOP; 00202 xdata at 0xE6DC volatile BYTE EP4GPIFTRIG; 00203 xdata at 0xE6E2 volatile BYTE EP6GPIFFLGSEL; 00204 xdata at 0xE6E3 volatile BYTE EP6GPIFPFSTOP; 00205 xdata at 0xE6E4 volatile BYTE EP6GPIFTRIG; 00206 xdata at 0xE6EA volatile BYTE EP8GPIFFLGSEL; 00207 xdata at 0xE6EB volatile BYTE EP8GPIFPFSTOP; 00208 xdata at 0xE6EC volatile BYTE EP8GPIFTRIG; 00209 xdata at 0xE6F0 volatile BYTE XGPIFSGLDATH; 00210 xdata at 0xE6F1 volatile BYTE XGPIFSGLDATLX; 00211 xdata at 0xE6F2 volatile BYTE XGPIFSGLDATLNOX; 00212 xdata at 0xE6F3 volatile BYTE GPIFREADYCFG; 00213 xdata at 0xE6F4 volatile BYTE GPIFREADYSTAT; 00214 xdata at 0xE6F5 volatile BYTE GPIFABORT; 00215 00216 // UDMA 00217 00218 xdata at 0xE6C6 volatile BYTE FLOWSTATE; 00219 xdata at 0xE6C7 volatile BYTE FLOWLOGIC; 00220 xdata at 0xE6C8 volatile BYTE FLOWEQ0CTL; 00221 xdata at 0xE6C9 volatile BYTE FLOWEQ1CTL; 00222 xdata at 0xE6CA volatile BYTE FLOWHOLDOFF; 00223 xdata at 0xE6CB volatile BYTE FLOWSTB; 00224 xdata at 0xE6CC volatile BYTE FLOWSTBEDGE; 00225 xdata at 0xE6CD volatile BYTE FLOWSTBHPERIOD; 00226 xdata at 0xE60C volatile BYTE GPIFHOLDAMOUNT; 00227 xdata at 0xE67D volatile BYTE UDMACRCH; 00228 xdata at 0xE67E volatile BYTE UDMACRCL; 00229 xdata at 0xE67F volatile BYTE UDMACRCQUAL; 00230 00231 // Endpoint Buffers 00232 00233 xdata at 0xE740 volatile BYTE EP0BUF[64]; 00234 xdata at 0xE780 volatile BYTE EP1OUTBUF[64]; 00235 xdata at 0xE7C0 volatile BYTE EP1INBUF[64]; 00236 xdata at 0xF000 volatile BYTE EP2FIFOBUF[1024]; 00237 xdata at 0xF400 volatile BYTE EP4FIFOBUF[1024]; 00238 xdata at 0xF800 volatile BYTE EP6FIFOBUF[1024]; 00239 xdata at 0xFC00 volatile BYTE EP8FIFOBUF[1024]; 00240 00241 // Error Correction Code (ECC) Registers (FX2LP/FX1 only) 00242 00243 xdata at 0xE628 volatile BYTE ECCCFG; 00244 xdata at 0xE629 volatile BYTE ECCRESET; 00245 xdata at 0xE62A volatile BYTE ECC1B0; 00246 xdata at 0xE62B volatile BYTE ECC1B1; 00247 xdata at 0xE62C volatile BYTE ECC1B2; 00248 xdata at 0xE62D volatile BYTE ECC2B0; 00249 xdata at 0xE62E volatile BYTE ECC2B1; 00250 xdata at 0xE62F volatile BYTE ECC2B2; 00251 00252 // Feature Registers (FX2LP/FX1 only) 00253 xdata at 0xE50D volatile BYTE GPCR2; 00254 00264 sfr at 0x80 IOA; 00265 /* IOA */ 00266 sbit at 0x80 + 0 PA0; 00267 sbit at 0x80 + 1 PA1; 00268 sbit at 0x80 + 2 PA2; 00269 sbit at 0x80 + 3 PA3; 00270 sbit at 0x80 + 4 PA4; 00271 sbit at 0x80 + 5 PA5; 00272 sbit at 0x80 + 6 PA6; 00273 sbit at 0x80 + 7 PA7; 00274 sfr at 0x81 SP; 00275 sfr at 0x82 DPL; 00276 sfr at 0x83 DPH; 00277 sfr at 0x84 DPL1; 00278 sfr at 0x85 DPH1; 00279 sfr at 0x86 DPS; 00280 sfr at 0x87 PCON; 00281 sfr at 0x88 TCON; 00282 /* TCON */ 00283 sbit at 0x88+0 IT0; 00284 sbit at 0x88+1 IE0; 00285 sbit at 0x88+2 IT1; 00286 sbit at 0x88+3 IE1; 00287 sbit at 0x88+4 TR0; 00288 sbit at 0x88+5 TF0; 00289 sbit at 0x88+6 TR1; 00290 sbit at 0x88+7 TF1; 00291 sfr at 0x89 TMOD; 00292 sfr at 0x8A TL0; 00293 sfr at 0x8B TL1; 00294 sfr at 0x8C TH0; 00295 sfr at 0x8D TH1; 00296 sfr at 0x8E CKCON; 00297 sfr at 0x90 IOB; 00298 /* IOB */ 00299 sbit at 0x90 + 0 PB0; 00300 sbit at 0x90 + 1 PB1; 00301 sbit at 0x90 + 2 PB2; 00302 sbit at 0x90 + 3 PB3; 00303 sbit at 0x90 + 4 PB4; 00304 sbit at 0x90 + 5 PB5; 00305 sbit at 0x90 + 6 PB6; 00306 sbit at 0x90 + 7 PB7; 00307 sfr at 0x91 EXIF; 00308 00309 //sfr at 0x92 MPAGE; 00310 sfr at 0x92 _XPAGE; // same as MPAGE for pdata sfr access w/ sdcc 00311 sfr at 0x98 SCON0; 00312 /* SCON0 */ 00313 sbit at 0x98+0 RI; 00314 sbit at 0x98+1 TI; 00315 sbit at 0x98+2 RB8; 00316 sbit at 0x98+3 TB8; 00317 sbit at 0x98+4 REN; 00318 sbit at 0x98+5 SM2; 00319 sbit at 0x98+6 SM1; 00320 sbit at 0x98+7 SM0; 00321 sfr at 0x99 SBUF0; 00322 00323 sfr at 0x9A AUTOPTRH1; 00324 sfr at 0x9B AUTOPTRL1; 00325 sfr at 0x9D AUTOPTRH2; 00326 sfr at 0x9E AUTOPTRL2; 00327 00328 sfr at 0xA0 IOC; 00329 /* IOC */ 00330 sbit at 0xA0 + 0 PC0; 00331 sbit at 0xA0 + 1 PC1; 00332 sbit at 0xA0 + 2 PC2; 00333 sbit at 0xA0 + 3 PC3; 00334 sbit at 0xA0 + 4 PC4; 00335 sbit at 0xA0 + 5 PC5; 00336 sbit at 0xA0 + 6 PC6; 00337 sbit at 0xA0 + 7 PC7; 00338 sfr at 0xA1 INT2CLR; 00339 sfr at 0xA2 INT4CLR; 00340 00341 sfr at 0xA8 IE; 00342 /* IE */ 00343 sbit at 0xA8+0 EX0; 00344 sbit at 0xA8+1 ET0; 00345 sbit at 0xA8+2 EX1; 00346 sbit at 0xA8+3 ET1; 00347 sbit at 0xA8+4 ES0; 00348 sbit at 0xA8+5 ET2; 00349 sbit at 0xA8+6 ES1; 00350 sbit at 0xA8+7 EA; 00351 00352 sfr at 0xAA EP2468STAT; 00353 sfr at 0xAB EP24FIFOFLGS; 00354 sfr at 0xAC EP68FIFOFLGS; 00355 sfr at 0xAF AUTOPTRSETUP; 00356 sfr at 0xB0 IOD; 00357 /* IOD */ 00358 sbit at 0xB0 + 0 PD0; 00359 sbit at 0xB0 + 1 PD1; 00360 sbit at 0xB0 + 2 PD2; 00361 sbit at 0xB0 + 3 PD3; 00362 sbit at 0xB0 + 4 PD4; 00363 sbit at 0xB0 + 5 PD5; 00364 sbit at 0xB0 + 6 PD6; 00365 sbit at 0xB0 + 7 PD7; 00366 sfr at 0xB1 IOE; 00367 sfr at 0xB2 OEA; 00368 sfr at 0xB3 OEB; 00369 sfr at 0xB4 OEC; 00370 sfr at 0xB5 OED; 00371 sfr at 0xB6 OEE; 00372 00373 sfr at 0xB8 IP; 00374 /* IP */ 00375 sbit at 0xB8+0 PX0; 00376 sbit at 0xB8+1 PT0; 00377 sbit at 0xB8+2 PX1; 00378 sbit at 0xB8+3 PT1; 00379 sbit at 0xB8+4 PS0; 00380 sbit at 0xB8+5 PT2; 00381 sbit at 0xB8+6 PS1; 00382 00383 sfr at 0xBA EP01STAT; 00384 sfr at 0xBB GPIFTRIG; 00385 00386 sfr at 0xBD GPIFSGLDATH; 00387 sfr at 0xBE GPIFSGLDATLX; 00388 sfr at 0xBF GPIFSGLDATLNOX; 00389 00390 sfr at 0xC0 SCON1; 00391 /* SCON1 */ 00392 sbit at 0xC0+0 RI1; 00393 sbit at 0xC0+1 TI1; 00394 sbit at 0xC0+2 RB81; 00395 sbit at 0xC0+3 TB81; 00396 sbit at 0xC0+4 REN1; 00397 sbit at 0xC0+5 SM21; 00398 sbit at 0xC0+6 SM11; 00399 sbit at 0xC0+7 SM01; 00400 sfr at 0xC1 SBUF1; 00401 sfr at 0xC8 T2CON; 00402 /* T2CON */ 00403 sbit at 0xC8+0 CP_RL2; 00404 sbit at 0xC8+1 C_T2; 00405 sbit at 0xC8+2 TR2; 00406 sbit at 0xC8+3 EXEN2; 00407 sbit at 0xC8+4 TCLK; 00408 sbit at 0xC8+5 RCLK; 00409 sbit at 0xC8+6 EXF2; 00410 sbit at 0xC8+7 TF2; 00411 sfr at 0xCA RCAP2L; 00412 sfr at 0xCB RCAP2H; 00413 sfr at 0xCC TL2; 00414 sfr at 0xCD TH2; 00415 sfr at 0xD0 PSW; 00416 /* PSW */ 00417 sbit at 0xD0+0 P; 00418 sbit at 0xD0+1 FL; 00419 sbit at 0xD0+2 OV; 00420 sbit at 0xD0+3 RS0; 00421 sbit at 0xD0+4 RS1; 00422 sbit at 0xD0+5 F0; 00423 sbit at 0xD0+6 AC; 00424 sbit at 0xD0+7 CY; 00425 sfr at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320 00426 /* EICON */ 00427 sbit at 0xD8+3 INT6; 00428 sbit at 0xD8+4 RESI; 00429 sbit at 0xD8+5 ERESI; 00430 sbit at 0xD8+7 SMOD1; 00431 sfr at 0xE0 ACC; 00432 sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320 00433 /* EIE */ 00434 sbit at 0xE8+0 EUSB; 00435 sbit at 0xE8+1 EI2C; 00436 sbit at 0xE8+2 EIEX4; 00437 sbit at 0xE8+3 EIEX5; 00438 sbit at 0xE8+4 EIEX6; 00439 sfr at 0xF0 B; 00440 sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320 00441 /* EIP */ 00442 sbit at 0xF8+0 PUSB; 00443 sbit at 0xF8+1 PI2C; 00444 sbit at 0xF8+2 EIPX4; 00445 sbit at 0xF8+3 EIPX5; 00446 sbit at 0xF8+4 EIPX6; 00447 00448 00449 /* CPU Control & Status Register (CPUCS) */ 00450 #define bmPRTCSTB bmBIT5 00451 #define bmCLKSPD (bmBIT4 | bmBIT3) 00452 #define bmCLKSPD1 bmBIT4 00453 #define bmCLKSPD0 bmBIT3 00454 #define bmCLKINV bmBIT2 00455 #define bmCLKOE bmBIT1 00456 #define bm8051RES bmBIT0 00457 /* Port Alternate Configuration Registers */ 00458 /* Port A (PORTACFG) */ 00459 #define bmFLAGD bmBIT7 00460 #define bmINT1 bmBIT1 00461 #define bmINT0 bmBIT0 00462 /* Port C (PORTCCFG) */ 00463 #define bmGPIFA7 bmBIT7 00464 #define bmGPIFA6 bmBIT6 00465 #define bmGPIFA5 bmBIT5 00466 #define bmGPIFA4 bmBIT4 00467 #define bmGPIFA3 bmBIT3 00468 #define bmGPIFA2 bmBIT2 00469 #define bmGPIFA1 bmBIT1 00470 #define bmGPIFA0 bmBIT0 00471 /* Port E (PORTECFG) */ 00472 #define bmGPIFA8 bmBIT7 00473 #define bmT2EX bmBIT6 00474 #define bmINT6 bmBIT5 00475 #define bmRXD1OUT bmBIT4 00476 #define bmRXD0OUT bmBIT3 00477 #define bmT2OUT bmBIT2 00478 #define bmT1OUT bmBIT1 00479 #define bmT0OUT bmBIT0 00480 00481 /* I2C Control & Status Register (I2CS) */ 00482 #define bmSTART bmBIT7 00483 #define bmSTOP bmBIT6 00484 #define bmLASTRD bmBIT5 00485 #define bmID (bmBIT4 | bmBIT3) 00486 #define bmBERR bmBIT2 00487 #define bmACK bmBIT1 00488 #define bmDONE bmBIT0 00489 /* I2C Control Register (I2CTL) */ 00490 #define bmSTOPIE bmBIT1 00491 #define bm400KHZ bmBIT0 00492 /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */ 00493 #define bmIV4 bmBIT6 00494 #define bmIV3 bmBIT5 00495 #define bmIV2 bmBIT4 00496 #define bmIV1 bmBIT3 00497 #define bmIV0 bmBIT2 00498 /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */ 00499 #define bmEP0ACK bmBIT6 00500 #define bmHSGRANT bmBIT5 00501 #define bmURES bmBIT4 00502 #define bmSUSP bmBIT3 00503 #define bmSUTOK bmBIT2 00504 #define bmSOF bmBIT1 00505 #define bmSUDAV bmBIT0 00506 /* USBERRIE/IRQ */ 00507 #define bmERRLIMIT bmBIT0 00508 #define bmISOEP2 bmBIT4 00509 #define bmISOEP4 bmBIT5 00510 #define bmISOEP6 bmBIT6 00511 #define bmISOEP8 bmBIT7 00512 00513 /* Endpoint Interrupt & Enable Registers (EPIE/EPIRQ) */ 00514 #define bmEP0IN bmBIT0 00515 #define bmEP0OUT bmBIT1 00516 #define bmEP1IN bmBIT2 00517 #define bmEP1OUT bmBIT3 00518 #define bmEP2 bmBIT4 00519 #define bmEP4 bmBIT5 00520 #define bmEP6 bmBIT6 00521 #define bmEP8 bmBIT7 00522 /* Breakpoint register (BREAKPT) */ 00523 #define bmBREAK bmBIT3 00524 #define bmBPPULSE bmBIT2 00525 #define bmBPEN bmBIT1 00526 /* Interrupt 2 & 4 Setup (INTSETUP) */ 00527 #define bmAV2EN bmBIT3 00528 #define INT4IN bmBIT1 00529 #define bmAV4EN bmBIT0 00530 /* USB Control & Status Register (USBCS) */ 00531 #define bmHSM bmBIT7 00532 #define bmDISCON bmBIT3 00533 #define bmNOSYNSOF bmBIT2 00534 #define bmRENUM bmBIT1 00535 #define bmSIGRESUME bmBIT0 00536 /* Wakeup Control and Status Register (WAKEUPCS) */ 00537 #define bmWU2 bmBIT7 00538 #define bmWU bmBIT6 00539 #define bmWU2POL bmBIT5 00540 #define bmWUPOL bmBIT4 00541 #define bmDPEN bmBIT2 00542 #define bmWU2EN bmBIT1 00543 #define bmWUEN bmBIT0 00544 /* End Point 0 Control & Status Register (EP0CS) */ 00545 #define bmHSNAK bmBIT7 00546 /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */ 00547 #define bmEPBUSY bmBIT1 00548 #define bmEPSTALL bmBIT0 00549 /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */ 00550 #define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4) 00551 #define bmEPFULL bmBIT3 00552 #define bmEPEMPTY bmBIT2 00553 /* Endpoint Status (EP2468STAT) SFR bits */ 00554 #define bmEP8FULL bmBIT7 00555 #define bmEP8EMPTY bmBIT6 00556 #define bmEP6FULL bmBIT5 00557 #define bmEP6EMPTY bmBIT4 00558 #define bmEP4FULL bmBIT3 00559 #define bmEP4EMPTY bmBIT2 00560 #define bmEP2FULL bmBIT1 00561 #define bmEP2EMPTY bmBIT0 00562 /* Endpoint Config (EP[24]CFG) */ 00563 #define bmBUF (bmBIT0|bmBIT1) 00564 /* Endpoint Config (EP[2468]CFG) */ 00565 #define bmSIZE bmBIT3 00566 #define bmTYPE (bmBIT4|bmBIT5) 00567 #define bmDIR bmBIT6 00568 #define bmVALID bmBIT7 00569 /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */ 00570 #define bmSDPAUTO bmBIT0 00571 /* Endpoint Data Toggle Control (TOGCTL) */ 00572 #define bmQUERYTOGGLE bmBIT7 00573 #define bmSETTOGGLE bmBIT6 00574 #define bmRESETTOGGLE bmBIT5 00575 #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0 00576 /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */ 00577 #define bmEP8IBN bmBIT5 00578 #define bmEP6IBN bmBIT4 00579 #define bmEP4IBN bmBIT3 00580 #define bmEP2IBN bmBIT2 00581 #define bmEP1IBN bmBIT1 00582 #define bmEP0IBN bmBIT0 00583 00584 /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */ 00585 #define bmEP8PING bmBIT7 00586 #define bmEP6PING bmBIT6 00587 #define bmEP4PING bmBIT5 00588 #define bmEP2PING bmBIT4 00589 #define bmEP1PING bmBIT3 00590 #define bmEP0PING bmBIT2 00591 #define bmIBN bmBIT0 00592 00593 /* Interface Configuration bits (IFCONFIG) */ 00594 #define bmIFCLKSRC bmBIT7 00595 #define bm3048MHZ bmBIT6 00596 #define bmIFCLKOE bmBIT5 00597 #define bmIFCLKPOL bmBIT4 00598 #define bmASYNC bmBIT3 00599 #define bmGSTATE bmBIT2 00600 #define bmIFCFG1 bmBIT1 00601 #define bmIFCFG0 bmBIT0 00602 #define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1) 00603 #define bmIFGPIF bmIFCFG1 00604 00605 /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */ 00606 #define bmINFM bmBIT6 00607 #define bmOEP bmBIT5 00608 #define bmAUTOOUT bmBIT4 00609 #define bmAUTOIN bmBIT3 00610 #define bmZEROLENIN bmBIT2 00611 #define bmWORDWIDE bmBIT0 00612 00613 /* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic 00614 features */ 00615 #define bmNOAUTOARM bmBIT1 00616 #define bmSKIPCOMMIT bmBIT0 00617 00618 /* Fifo Reset bits (FIFORESET) */ 00619 #define bmNAKALL bmBIT7 00620 00621 /* Chip Feature Register (GPCR2) */ 00622 #define bmFULLSPEEDONLY bmBIT4 00623 00624 #endif /* FX2REGS_H */
1.5.7.1