include/fx2regs.h File Reference

#include "fx2types.h"

Go to the source code of this file.

Defines
#define	EXTAUTODAT1   XAUTODAT1
	Autoptr2 MOVX access.
#define	EXTAUTODAT2   XAUTODAT2
#define	bmPRTCSTB   bmBIT5
#define	bmCLKSPD   (bmBIT4 | bmBIT3)
#define	bmCLKSPD1   bmBIT4
#define	bmCLKSPD0   bmBIT3
#define	bmCLKINV   bmBIT2
#define	bmCLKOE   bmBIT1
#define	bm8051RES   bmBIT0
#define	bmFLAGD   bmBIT7
#define	bmINT1   bmBIT1
#define	bmINT0   bmBIT0
#define	bmGPIFA7   bmBIT7
#define	bmGPIFA6   bmBIT6
#define	bmGPIFA5   bmBIT5
#define	bmGPIFA4   bmBIT4
#define	bmGPIFA3   bmBIT3
#define	bmGPIFA2   bmBIT2
#define	bmGPIFA1   bmBIT1
#define	bmGPIFA0   bmBIT0
#define	bmGPIFA8   bmBIT7
#define	bmT2EX   bmBIT6
#define	bmINT6   bmBIT5
#define	bmRXD1OUT   bmBIT4
#define	bmRXD0OUT   bmBIT3
#define	bmT2OUT   bmBIT2
#define	bmT1OUT   bmBIT1
#define	bmT0OUT   bmBIT0
#define	bmSTART   bmBIT7
#define	bmSTOP   bmBIT6
#define	bmLASTRD   bmBIT5
#define	bmID   (bmBIT4 | bmBIT3)
#define	bmBERR   bmBIT2
#define	bmACK   bmBIT1
#define	bmDONE   bmBIT0
#define	bmSTOPIE   bmBIT1
#define	bm400KHZ   bmBIT0
#define	bmIV4   bmBIT6
#define	bmIV3   bmBIT5
#define	bmIV2   bmBIT4
#define	bmIV1   bmBIT3
#define	bmIV0   bmBIT2
#define	bmEP0ACK   bmBIT6
#define	bmHSGRANT   bmBIT5
#define	bmURES   bmBIT4
#define	bmSUSP   bmBIT3
#define	bmSUTOK   bmBIT2
#define	bmSOF   bmBIT1
#define	bmSUDAV   bmBIT0
#define	bmERRLIMIT   bmBIT0
#define	bmISOEP2   bmBIT4
#define	bmISOEP4   bmBIT5
#define	bmISOEP6   bmBIT6
#define	bmISOEP8   bmBIT7
#define	bmEP0IN   bmBIT0
#define	bmEP0OUT   bmBIT1
#define	bmEP1IN   bmBIT2
#define	bmEP1OUT   bmBIT3
#define	bmEP2   bmBIT4
#define	bmEP4   bmBIT5
#define	bmEP6   bmBIT6
#define	bmEP8   bmBIT7
#define	bmBREAK   bmBIT3
#define	bmBPPULSE   bmBIT2
#define	bmBPEN   bmBIT1
#define	bmAV2EN   bmBIT3
#define	INT4IN   bmBIT1
#define	bmAV4EN   bmBIT0
#define	bmHSM   bmBIT7
#define	bmDISCON   bmBIT3
#define	bmNOSYNSOF   bmBIT2
#define	bmRENUM   bmBIT1
#define	bmSIGRESUME   bmBIT0
#define	bmWU2   bmBIT7
#define	bmWU   bmBIT6
#define	bmWU2POL   bmBIT5
#define	bmWUPOL   bmBIT4
#define	bmDPEN   bmBIT2
#define	bmWU2EN   bmBIT1
#define	bmWUEN   bmBIT0
#define	bmHSNAK   bmBIT7
#define	bmEPBUSY   bmBIT1
#define	bmEPSTALL   bmBIT0
#define	bmNPAK   (bmBIT6 | bmBIT5 | bmBIT4)
#define	bmEPFULL   bmBIT3
#define	bmEPEMPTY   bmBIT2
#define	bmEP8FULL   bmBIT7
#define	bmEP8EMPTY   bmBIT6
#define	bmEP6FULL   bmBIT5
#define	bmEP6EMPTY   bmBIT4
#define	bmEP4FULL   bmBIT3
#define	bmEP4EMPTY   bmBIT2
#define	bmEP2FULL   bmBIT1
#define	bmEP2EMPTY   bmBIT0
#define	bmBUF   (bmBIT0|bmBIT1)
#define	bmSIZE   bmBIT3
#define	bmTYPE   (bmBIT4|bmBIT5)
#define	bmDIR   bmBIT6
#define	bmVALID   bmBIT7
#define	bmSDPAUTO   bmBIT0
#define	bmQUERYTOGGLE   bmBIT7
#define	bmSETTOGGLE   bmBIT6
#define	bmRESETTOGGLE   bmBIT5
#define	bmTOGCTLEPMASK   bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
#define	bmEP8IBN   bmBIT5
#define	bmEP6IBN   bmBIT4
#define	bmEP4IBN   bmBIT3
#define	bmEP2IBN   bmBIT2
#define	bmEP1IBN   bmBIT1
#define	bmEP0IBN   bmBIT0
#define	bmEP8PING   bmBIT7
#define	bmEP6PING   bmBIT6
#define	bmEP4PING   bmBIT5
#define	bmEP2PING   bmBIT4
#define	bmEP1PING   bmBIT3
#define	bmEP0PING   bmBIT2
#define	bmIBN   bmBIT0
#define	bmIFCLKSRC   bmBIT7
#define	bm3048MHZ   bmBIT6
#define	bmIFCLKOE   bmBIT5
#define	bmIFCLKPOL   bmBIT4
#define	bmASYNC   bmBIT3
#define	bmGSTATE   bmBIT2
#define	bmIFCFG1   bmBIT1
#define	bmIFCFG0   bmBIT0
#define	bmIFCFGMASK   (bmIFCFG0 | bmIFCFG1)
#define	bmIFGPIF   bmIFCFG1
#define	bmINFM   bmBIT6
#define	bmOEP   bmBIT5
#define	bmAUTOOUT   bmBIT4
#define	bmAUTOIN   bmBIT3
#define	bmZEROLENIN   bmBIT2
#define	bmWORDWIDE   bmBIT0
#define	bmNOAUTOARM   bmBIT1
#define	bmSKIPCOMMIT   bmBIT0
#define	bmNAKALL   bmBIT7
#define	bmFULLSPEEDONLY   bmBIT4
Variables
xdata at volatile BYTE	GPIF_WAVE_DATA
xdata at volatile BYTE	RES_WAVEDATA_END
xdata at volatile BYTE	CPUCS
xdata at volatile BYTE	IFCONFIG
	Control & Status.
xdata at volatile BYTE	PINFLAGSAB
	Interface Configuration.
xdata at volatile BYTE	PINFLAGSCD
	FIFO FLAGA and FLAGB Assignments.
xdata at volatile BYTE	FIFORESET
	FIFO FLAGC and FLAGD Assignments.
xdata at volatile BYTE	BREAKPT
	Restore FIFOS to default state.
xdata at volatile BYTE	BPADDRH
	Breakpoint.
xdata at volatile BYTE	BPADDRL
	Breakpoint Address H.
xdata at volatile BYTE	UART230
	Breakpoint Address L.
xdata at volatile BYTE	FIFOPINPOLAR
	230 Kbaud clock for T0,T1,T2
xdata at volatile BYTE	REVID
	FIFO polarities.
xdata at volatile BYTE	REVCTL
	Chip Revision.
xdata at volatile BYTE	EP1OUTCFG
	Chip Revision Control.
xdata at volatile BYTE	EP1INCFG
	Endpoint 1-OUT Configuration.
xdata at volatile BYTE	EP2CFG
	Endpoint 1-IN Configuration.
xdata at volatile BYTE	EP4CFG
	Endpoint 2 Configuration.
xdata at volatile BYTE	EP6CFG
	Endpoint 4 Configuration.
xdata at volatile BYTE	EP8CFG
	Endpoint 6 Configuration.
xdata at volatile BYTE	EP2FIFOCFG
	Endpoint 8 Configuration.
xdata at volatile BYTE	EP4FIFOCFG
	Endpoint 2 FIFO configuration.
xdata at volatile BYTE	EP6FIFOCFG
	Endpoint 4 FIFO configuration.
xdata at volatile BYTE	EP8FIFOCFG
	Endpoint 6 FIFO configuration.
xdata at volatile BYTE	EP2AUTOINLENH
	Endpoint 8 FIFO configuration.
xdata at volatile BYTE	EP2AUTOINLENL
	Endpoint 2 Packet Length H (IN only).
xdata at volatile BYTE	EP4AUTOINLENH
	Endpoint 2 Packet Length L (IN only).
xdata at volatile BYTE	EP4AUTOINLENL
	Endpoint 4 Packet Length H (IN only).
xdata at volatile BYTE	EP6AUTOINLENH
	Endpoint 4 Packet Length L (IN only).
xdata at volatile BYTE	EP6AUTOINLENL
	Endpoint 6 Packet Length H (IN only).
xdata at volatile BYTE	EP8AUTOINLENH
	Endpoint 6 Packet Length L (IN only).
xdata at volatile BYTE	EP8AUTOINLENL
	Endpoint 8 Packet Length H (IN only).
xdata at volatile BYTE	EP2FIFOPFH
	Endpoint 8 Packet Length L (IN only).
xdata at volatile BYTE	EP2FIFOPFL
	EP2 Programmable Flag trigger H.
xdata at volatile BYTE	EP4FIFOPFH
	EP2 Programmable Flag trigger L.
xdata at volatile BYTE	EP4FIFOPFL
	EP4 Programmable Flag trigger H.
xdata at volatile BYTE	EP6FIFOPFH
	EP4 Programmable Flag trigger L.
xdata at volatile BYTE	EP6FIFOPFL
	EP6 Programmable Flag trigger H.
xdata at volatile BYTE	EP8FIFOPFH
	EP6 Programmable Flag trigger L.
xdata at volatile BYTE	EP8FIFOPFL
	EP8 Programmable Flag trigger H.
xdata at volatile BYTE	EP2ISOINPKTS
	EP8 Programmable Flag trigger L.
xdata at volatile BYTE	EP4ISOINPKTS
	EP2 (if ISO) IN Packets per frame (1-3).
xdata at volatile BYTE	EP6ISOINPKTS
	EP4 (if ISO) IN Packets per frame (1-3).
xdata at volatile BYTE	EP8ISOINPKTS
	EP6 (if ISO) IN Packets per frame (1-3).
xdata at volatile BYTE	INPKTEND
	EP8 (if ISO) IN Packets per frame (1-3).
xdata at volatile BYTE	OUTPKTEND
	Force IN Packet End.
xdata at volatile BYTE	EP2FIFOIE
	Force OUT Packet End.
xdata at volatile BYTE	EP2FIFOIRQ
	Endpoint 2 Flag Interrupt Enable.
xdata at volatile BYTE	EP4FIFOIE
	Endpoint 2 Flag Interrupt Request.
xdata at volatile BYTE	EP4FIFOIRQ
	Endpoint 4 Flag Interrupt Enable.
xdata at volatile BYTE	EP6FIFOIE
	Endpoint 4 Flag Interrupt Request.
xdata at volatile BYTE	EP6FIFOIRQ
	Endpoint 6 Flag Interrupt Enable.
xdata at volatile BYTE	EP8FIFOIE
	Endpoint 6 Flag Interrupt Request.
xdata at volatile BYTE	EP8FIFOIRQ
	Endpoint 8 Flag Interrupt Enable.
xdata at volatile BYTE	IBNIE
	Endpoint 8 Flag Interrupt Request.
xdata at volatile BYTE	IBNIRQ
	IN-BULK-NAK Interrupt Enable.
xdata at volatile BYTE	NAKIE
	IN-BULK-NAK interrupt Request.
xdata at volatile BYTE	NAKIRQ
	Endpoint Ping NAK interrupt Enable.
xdata at volatile BYTE	USBIE
	Endpoint Ping NAK interrupt Request.
xdata at volatile BYTE	USBIRQ
	USB Int Enables.
xdata at volatile BYTE	EPIE
	USB Interrupt Requests.
xdata at volatile BYTE	EPIRQ
	Endpoint Interrupt Enables.
xdata at volatile BYTE	GPIFIE
	Endpoint Interrupt Requests.
xdata at volatile BYTE	GPIFIRQ
	GPIF Interrupt Enable.
xdata at volatile BYTE	USBERRIE
	GPIF Interrupt Request.
xdata at volatile BYTE	USBERRIRQ
	USB Error Interrupt Enables.
xdata at volatile BYTE	ERRCNTLIM
	USB Error Interrupt Requests.
xdata at volatile BYTE	CLRERRCNT
	USB Error counter and limit.
xdata at volatile BYTE	INT2IVEC
	Clear Error Counter EC[3..0].
xdata at volatile BYTE	INT4IVEC
	Interupt 2 (USB) Autovector.
xdata at volatile BYTE	INTSETUP
	Interupt 4 (FIFOS & GPIF) Autovector.
xdata at volatile BYTE	PORTACFG
	Interrupt 2&4 Setup.
xdata at volatile BYTE	PORTCCFG
	I/O PORTA Alternate Configuration.
xdata at volatile BYTE	PORTECFG
	I/O PORTC Alternate Configuration.
xdata at volatile BYTE	I2CS
	I/O PORTE Alternate Configuration.
xdata at volatile BYTE	I2DAT
	Control & Status.
xdata at volatile BYTE	I2CTL
	Data.
xdata at volatile BYTE	XAUTODAT1
	I2C Control.
xdata at volatile BYTE	XAUTODAT2
	Autoptr1 MOVX access.
xdata at volatile BYTE	USBCS
xdata at volatile BYTE	SUSPEND
	USB Control & Status.
xdata at volatile BYTE	WAKEUPCS
	Put chip into suspend.
xdata at volatile BYTE	TOGCTL
	Wakeup source and polarity.
xdata at volatile BYTE	USBFRAMEH
	Toggle Control.
xdata at volatile BYTE	USBFRAMEL
	USB Frame count H.
xdata at volatile BYTE	MICROFRAME
	USB Frame count L.
xdata at volatile BYTE	FNADDR
	Microframe count, 0-7.
xdata at volatile BYTE	EP0BCH
	USB Function address.
xdata at volatile BYTE	EP0BCL
	Endpoint 0 Byte Count H.
xdata at volatile BYTE	EP1OUTBC
	Endpoint 0 Byte Count L.
xdata at volatile BYTE	EP1INBC
	Endpoint 1 OUT Byte Count.
xdata at volatile BYTE	EP2BCH
	Endpoint 1 IN Byte Count.
xdata at volatile BYTE	EP2BCL
	Endpoint 2 Byte Count H.
xdata at volatile BYTE	EP4BCH
	Endpoint 2 Byte Count L.
xdata at volatile BYTE	EP4BCL
	Endpoint 4 Byte Count H.
xdata at volatile BYTE	EP6BCH
	Endpoint 4 Byte Count L.
xdata at volatile BYTE	EP6BCL
	Endpoint 6 Byte Count H.
xdata at volatile BYTE	EP8BCH
	Endpoint 6 Byte Count L.
xdata at volatile BYTE	EP8BCL
	Endpoint 8 Byte Count H.
xdata at volatile BYTE	EP0CS
	Endpoint 8 Byte Count L.
xdata at volatile BYTE	EP1OUTCS
	Endpoint Control and Status.
xdata at volatile BYTE	EP1INCS
	Endpoint 1 OUT Control and Status.
xdata at volatile BYTE	EP2CS
	Endpoint 1 IN Control and Status.
xdata at volatile BYTE	EP4CS
	Endpoint 2 Control and Status.
xdata at volatile BYTE	EP6CS
	Endpoint 4 Control and Status.
xdata at volatile BYTE	EP8CS
	Endpoint 6 Control and Status.
xdata at volatile BYTE	EP2FIFOFLGS
	Endpoint 8 Control and Status.
xdata at volatile BYTE	EP4FIFOFLGS
	Endpoint 2 Flags.
xdata at volatile BYTE	EP6FIFOFLGS
	Endpoint 4 Flags.
xdata at volatile BYTE	EP8FIFOFLGS
	Endpoint 6 Flags.
xdata at volatile BYTE	EP2FIFOBCH
	Endpoint 8 Flags.
xdata at volatile BYTE	EP2FIFOBCL
	EP2 FIFO total byte count H.
xdata at volatile BYTE	EP4FIFOBCH
	EP2 FIFO total byte count L.
xdata at volatile BYTE	EP4FIFOBCL
	EP4 FIFO total byte count H.
xdata at volatile BYTE	EP6FIFOBCH
	EP4 FIFO total byte count L.
xdata at volatile BYTE	EP6FIFOBCL
	EP6 FIFO total byte count H.
xdata at volatile BYTE	EP8FIFOBCH
	EP6 FIFO total byte count L.
xdata at volatile BYTE	EP8FIFOBCL
	EP8 FIFO total byte count H.
xdata at volatile BYTE	SUDPTRH
	EP8 FIFO total byte count L.
xdata at volatile BYTE	SUDPTRL
	Setup Data Pointer high address byte.
xdata at volatile BYTE	SUDPTRCTL
	Setup Data Pointer low address byte.
xdata at volatile BYTE	SETUPDAT [8]
	Setup Data Pointer Auto Mode.
xdata at volatile BYTE	GPIFWFSELECT
	8 bytes of SETUP data
xdata at volatile BYTE	GPIFIDLECS
	Waveform Selector.
xdata at volatile BYTE	GPIFIDLECTL
	GPIF Done, GPIF IDLE drive mode.
xdata at volatile BYTE	GPIFCTLCFG
	Inactive Bus, CTL states.
xdata at volatile BYTE	GPIFADRH
	CTL OUT pin drive.
xdata at volatile BYTE	GPIFADRL
	GPIF Address H.
xdata at volatile BYTE	GPIFTCB3
	GPIF Address L.
xdata at volatile BYTE	GPIFTCB2
	GPIF Transaction Count Byte 3.
xdata at volatile BYTE	GPIFTCB1
	GPIF Transaction Count Byte 2.
xdata at volatile BYTE	GPIFTCB0
	GPIF Transaction Count Byte 1.
xdata at volatile BYTE	EP2GPIFFLGSEL
	GPIF Transaction Count Byte 0.
xdata at volatile BYTE	EP2GPIFPFSTOP
	EP2 GPIF Flag select.
xdata at volatile BYTE	EP2GPIFTRIG
	Stop GPIF EP2 transaction on prog. flag.
xdata at volatile BYTE	EP4GPIFFLGSEL
	EP2 FIFO Trigger.
xdata at volatile BYTE	EP4GPIFPFSTOP
	EP4 GPIF Flag select.
xdata at volatile BYTE	EP4GPIFTRIG
	Stop GPIF EP4 transaction on prog. flag.
xdata at volatile BYTE	EP6GPIFFLGSEL
	EP4 FIFO Trigger.
xdata at volatile BYTE	EP6GPIFPFSTOP
	EP6 GPIF Flag select.
xdata at volatile BYTE	EP6GPIFTRIG
	Stop GPIF EP6 transaction on prog. flag.
xdata at volatile BYTE	EP8GPIFFLGSEL
	EP6 FIFO Trigger.
xdata at volatile BYTE	EP8GPIFPFSTOP
	EP8 GPIF Flag select.
xdata at volatile BYTE	EP8GPIFTRIG
	Stop GPIF EP8 transaction on prog. flag.
xdata at volatile BYTE	XGPIFSGLDATH
	EP8 FIFO Trigger.
xdata at volatile BYTE	XGPIFSGLDATLX
	GPIF Data H (16-bit mode only).
xdata at volatile BYTE	XGPIFSGLDATLNOX
	Read/Write GPIF Data L & trigger transac.
xdata at volatile BYTE	GPIFREADYCFG
	Read GPIF Data L, no transac trigger.
xdata at volatile BYTE	GPIFREADYSTAT
	Internal RDY,Sync/Async, RDY5CFG.
xdata at volatile BYTE	GPIFABORT
	RDY pin states.
xdata at volatile BYTE	FLOWSTATE
	Abort GPIF cycles.
xdata at volatile BYTE	FLOWLOGIC
	Defines GPIF flow state.
xdata at volatile BYTE	FLOWEQ0CTL
	Defines flow/hold decision criteria.
xdata at volatile BYTE	FLOWEQ1CTL
	CTL states during active flow state.
xdata at volatile BYTE	FLOWHOLDOFF
	CTL states during hold flow state.
xdata at volatile BYTE	FLOWSTB
xdata at volatile BYTE	FLOWSTBEDGE
	CTL/RDY Signal to use as master data strobe.
xdata at volatile BYTE	FLOWSTBHPERIOD
	Defines active master strobe edge.
xdata at volatile BYTE	GPIFHOLDAMOUNT
	Half Period of output master strobe.
xdata at volatile BYTE	UDMACRCH
	Data delay shift.
xdata at volatile BYTE	UDMACRCL
	CRC Upper byte.
xdata at volatile BYTE	UDMACRCQUAL
	CRC Lower byte.
xdata at volatile BYTE	EP0BUF [64]
	UDMA In only, host terminated use only.
xdata at volatile BYTE	EP1OUTBUF [64]
	EP0 IN-OUT buffer.
xdata at volatile BYTE	EP1INBUF [64]
	EP1-OUT buffer.
xdata at volatile BYTE	EP2FIFOBUF [1024]
	EP1-IN buffer.
xdata at volatile BYTE	EP4FIFOBUF [1024]
	512/1024-byte EP2 buffer (IN or OUT)
xdata at volatile BYTE	EP6FIFOBUF [1024]
	512 byte EP4 buffer (IN or OUT)
xdata at volatile BYTE	EP8FIFOBUF [1024]
	512/1024-byte EP6 buffer (IN or OUT)
xdata at volatile BYTE	ECCCFG
	512 byte EP8 buffer (IN or OUT)
xdata at volatile BYTE	ECCRESET
	ECC Configuration.
xdata at volatile BYTE	ECC1B0
	ECC Reset.
xdata at volatile BYTE	ECC1B1
	ECC1 Byte 0.
xdata at volatile BYTE	ECC1B2
	ECC1 Byte 1.
xdata at volatile BYTE	ECC2B0
	ECC1 Byte 2.
xdata at volatile BYTE	ECC2B1
	ECC2 Byte 0.
xdata at volatile BYTE	ECC2B2
	ECC2 Byte 1.
xdata at volatile BYTE	GPCR2
	ECC2 Byte 2.
sfr at	IOA
	Chip Features.
sbit at	PA0
sbit at	PA1
sbit at	PA2
sbit at	PA3
sbit at	PA4
sbit at	PA5
sbit at	PA6
sbit at	PA7
sfr at	SP
sfr at	DPL
sfr at	DPH
sfr at	DPL1
sfr at	DPH1
sfr at	DPS
sfr at	PCON
sfr at	TCON
sbit at	IT0
sbit at	IE0
sbit at	IT1
sbit at	IE1
sbit at	TR0
sbit at	TF0
sbit at	TR1
sbit at	TF1
sfr at	TMOD
sfr at	TL0
sfr at	TL1
sfr at	TH0
sfr at	TH1
sfr at	CKCON
sfr at	IOB
sbit at	PB0
sbit at	PB1
sbit at	PB2
sbit at	PB3
sbit at	PB4
sbit at	PB5
sbit at	PB6
sbit at	PB7
sfr at	EXIF
sfr at	_XPAGE
sfr at	SCON0
sbit at	RI
sbit at	TI
sbit at	RB8
sbit at	TB8
sbit at	REN
sbit at	SM2
sbit at	SM1
sbit at	SM0
sfr at	SBUF0
sfr at	AUTOPTRH1
sfr at	AUTOPTRL1
sfr at	AUTOPTRH2
sfr at	AUTOPTRL2
sfr at	IOC
sbit at	PC0
sbit at	PC1
sbit at	PC2
sbit at	PC3
sbit at	PC4
sbit at	PC5
sbit at	PC6
sbit at	PC7
sfr at	INT2CLR
sfr at	INT4CLR
sfr at	IE
sbit at	EX0
sbit at	ET0
sbit at	EX1
sbit at	ET1
sbit at	ES0
sbit at	ET2
sbit at	ES1
sbit at	EA
sfr at	EP2468STAT
sfr at	EP24FIFOFLGS
sfr at	EP68FIFOFLGS
sfr at	AUTOPTRSETUP
sfr at	IOD
sbit at	PD0
sbit at	PD1
sbit at	PD2
sbit at	PD3
sbit at	PD4
sbit at	PD5
sbit at	PD6
sbit at	PD7
sfr at	IOE
sfr at	OEA
sfr at	OEB
sfr at	OEC
sfr at	OED
sfr at	OEE
sfr at	IP
sbit at	PX0
sbit at	PT0
sbit at	PX1
sbit at	PT1
sbit at	PS0
sbit at	PT2
sbit at	PS1
sfr at	EP01STAT
sfr at	GPIFTRIG
sfr at	GPIFSGLDATH
sfr at	GPIFSGLDATLX
sfr at	GPIFSGLDATLNOX
sfr at	SCON1
sbit at	RI1
sbit at	TI1
sbit at	RB81
sbit at	TB81
sbit at	REN1
sbit at	SM21
sbit at	SM11
sbit at	SM01
sfr at	SBUF1
sfr at	T2CON
sbit at	CP_RL2
sbit at	C_T2
sbit at	TR2
sbit at	EXEN2
sbit at	TCLK
sbit at	RCLK
sbit at	EXF2
sbit at	TF2
sfr at	RCAP2L
sfr at	RCAP2H
sfr at	TL2
sfr at	TH2
sfr at	PSW
sbit at	P
sbit at	FL
sbit at	OV
sbit at	RS0
sbit at	RS1
sbit at	F0
sbit at	AC
sbit at	CY
sfr at	EICON
sbit at	INT6
sbit at	RESI
sbit at	ERESI
sbit at	SMOD1
sfr at	ACC
sfr at	EIE
sbit at	EUSB
sbit at	EI2C
sbit at	EIEX4
sbit at	EIEX5
sbit at	EIEX6
sfr at	B
sfr at	EIP
sbit at	PUSB
sbit at	PI2C
sbit at	EIPX4
sbit at	EIPX5
sbit at	EIPX6

---

Detailed Description

This is the basic header/register file for working with the cypress fx2 (cyc768013) and variants 8051 chipset. It contains the special function register definitions as well as the special configuration registers addresses.

The TRM for the fx2 chip contains the full documentation for what each of these registers do.

Definition in file fx2regs.h.

---

Define Documentation

#define bm3048MHZ   bmBIT6

Definition at line 595 of file fx2regs.h.

#define bm400KHZ   bmBIT0

Definition at line 491 of file fx2regs.h.

#define bm8051RES   bmBIT0

Definition at line 456 of file fx2regs.h.

#define bmACK   bmBIT1

Definition at line 487 of file fx2regs.h.

#define bmASYNC   bmBIT3

Definition at line 598 of file fx2regs.h.

#define bmAUTOIN   bmBIT3

Definition at line 609 of file fx2regs.h.

#define bmAUTOOUT   bmBIT4

Definition at line 608 of file fx2regs.h.

#define bmAV2EN   bmBIT3

Definition at line 527 of file fx2regs.h.

#define bmAV4EN   bmBIT0

Definition at line 529 of file fx2regs.h.

#define bmBERR   bmBIT2

Definition at line 486 of file fx2regs.h.

#define bmBPEN   bmBIT1

Definition at line 525 of file fx2regs.h.

#define bmBPPULSE   bmBIT2

Definition at line 524 of file fx2regs.h.

#define bmBREAK   bmBIT3

Definition at line 523 of file fx2regs.h.

#define bmBUF   (bmBIT0|bmBIT1)

Definition at line 563 of file fx2regs.h.

#define bmCLKINV   bmBIT2

Definition at line 454 of file fx2regs.h.

#define bmCLKOE   bmBIT1

Definition at line 455 of file fx2regs.h.

#define bmCLKSPD   (bmBIT4 | bmBIT3)

Definition at line 451 of file fx2regs.h.

#define bmCLKSPD0   bmBIT3

Definition at line 453 of file fx2regs.h.

#define bmCLKSPD1   bmBIT4

Definition at line 452 of file fx2regs.h.

#define bmDIR   bmBIT6

Definition at line 567 of file fx2regs.h.

#define bmDISCON   bmBIT3

Definition at line 532 of file fx2regs.h.

#define bmDONE   bmBIT0

Definition at line 488 of file fx2regs.h.

#define bmDPEN   bmBIT2

Definition at line 541 of file fx2regs.h.

#define bmEP0ACK   bmBIT6

Definition at line 499 of file fx2regs.h.

#define bmEP0IBN   bmBIT0

Definition at line 582 of file fx2regs.h.

#define bmEP0IN   bmBIT0

Definition at line 514 of file fx2regs.h.

#define bmEP0OUT   bmBIT1

Definition at line 515 of file fx2regs.h.

#define bmEP0PING   bmBIT2

Definition at line 590 of file fx2regs.h.

#define bmEP1IBN   bmBIT1

Definition at line 581 of file fx2regs.h.

#define bmEP1IN   bmBIT2

Definition at line 516 of file fx2regs.h.

#define bmEP1OUT   bmBIT3

Definition at line 517 of file fx2regs.h.

#define bmEP1PING   bmBIT3

Definition at line 589 of file fx2regs.h.

#define bmEP2   bmBIT4

Definition at line 518 of file fx2regs.h.

#define bmEP2EMPTY   bmBIT0

Definition at line 561 of file fx2regs.h.

#define bmEP2FULL   bmBIT1

Definition at line 560 of file fx2regs.h.

#define bmEP2IBN   bmBIT2

Definition at line 580 of file fx2regs.h.

#define bmEP2PING   bmBIT4

Definition at line 588 of file fx2regs.h.

#define bmEP4   bmBIT5

Definition at line 519 of file fx2regs.h.

#define bmEP4EMPTY   bmBIT2

Definition at line 559 of file fx2regs.h.

#define bmEP4FULL   bmBIT3

Definition at line 558 of file fx2regs.h.

#define bmEP4IBN   bmBIT3

Definition at line 579 of file fx2regs.h.

#define bmEP4PING   bmBIT5

Definition at line 587 of file fx2regs.h.

#define bmEP6   bmBIT6

Definition at line 520 of file fx2regs.h.

#define bmEP6EMPTY   bmBIT4

Definition at line 557 of file fx2regs.h.

#define bmEP6FULL   bmBIT5

Definition at line 556 of file fx2regs.h.

#define bmEP6IBN   bmBIT4

Definition at line 578 of file fx2regs.h.

#define bmEP6PING   bmBIT6

Definition at line 586 of file fx2regs.h.

#define bmEP8   bmBIT7

Definition at line 521 of file fx2regs.h.

#define bmEP8EMPTY   bmBIT6

Definition at line 555 of file fx2regs.h.

#define bmEP8FULL   bmBIT7

Definition at line 554 of file fx2regs.h.

#define bmEP8IBN   bmBIT5

Definition at line 577 of file fx2regs.h.

#define bmEP8PING   bmBIT7

Definition at line 585 of file fx2regs.h.

#define bmEPBUSY   bmBIT1

Definition at line 547 of file fx2regs.h.

#define bmEPEMPTY   bmBIT2

Definition at line 552 of file fx2regs.h.

#define bmEPFULL   bmBIT3

Definition at line 551 of file fx2regs.h.

#define bmEPSTALL   bmBIT0

Definition at line 548 of file fx2regs.h.

#define bmERRLIMIT   bmBIT0

Definition at line 507 of file fx2regs.h.

#define bmFLAGD   bmBIT7

Definition at line 459 of file fx2regs.h.

#define bmFULLSPEEDONLY   bmBIT4

Definition at line 622 of file fx2regs.h.

#define bmGPIFA0   bmBIT0

Definition at line 470 of file fx2regs.h.

#define bmGPIFA1   bmBIT1

Definition at line 469 of file fx2regs.h.

#define bmGPIFA2   bmBIT2

Definition at line 468 of file fx2regs.h.

#define bmGPIFA3   bmBIT3

Definition at line 467 of file fx2regs.h.

#define bmGPIFA4   bmBIT4

Definition at line 466 of file fx2regs.h.

#define bmGPIFA5   bmBIT5

Definition at line 465 of file fx2regs.h.

#define bmGPIFA6   bmBIT6

Definition at line 464 of file fx2regs.h.

#define bmGPIFA7   bmBIT7

Definition at line 463 of file fx2regs.h.

#define bmGPIFA8   bmBIT7

Definition at line 472 of file fx2regs.h.

#define bmGSTATE   bmBIT2

Definition at line 599 of file fx2regs.h.

#define bmHSGRANT   bmBIT5

Definition at line 500 of file fx2regs.h.

#define bmHSM   bmBIT7

Definition at line 531 of file fx2regs.h.

#define bmHSNAK   bmBIT7

Definition at line 545 of file fx2regs.h.

#define bmIBN   bmBIT0

Definition at line 591 of file fx2regs.h.

#define bmID   (bmBIT4 | bmBIT3)

Definition at line 485 of file fx2regs.h.

#define bmIFCFG0   bmBIT0

Definition at line 601 of file fx2regs.h.

#define bmIFCFG1   bmBIT1

Definition at line 600 of file fx2regs.h.

#define bmIFCFGMASK   (bmIFCFG0 | bmIFCFG1)

Definition at line 602 of file fx2regs.h.

#define bmIFCLKOE   bmBIT5

Definition at line 596 of file fx2regs.h.

#define bmIFCLKPOL   bmBIT4

Definition at line 597 of file fx2regs.h.

#define bmIFCLKSRC   bmBIT7

Definition at line 594 of file fx2regs.h.

#define bmIFGPIF   bmIFCFG1

Definition at line 603 of file fx2regs.h.

#define bmINFM   bmBIT6

Definition at line 606 of file fx2regs.h.

#define bmINT0   bmBIT0

Definition at line 461 of file fx2regs.h.

#define bmINT1   bmBIT1

Definition at line 460 of file fx2regs.h.

#define bmINT6   bmBIT5

Definition at line 474 of file fx2regs.h.

#define bmISOEP2   bmBIT4

Definition at line 508 of file fx2regs.h.

#define bmISOEP4   bmBIT5

Definition at line 509 of file fx2regs.h.

#define bmISOEP6   bmBIT6

Definition at line 510 of file fx2regs.h.

#define bmISOEP8   bmBIT7

Definition at line 511 of file fx2regs.h.

#define bmIV0   bmBIT2

Definition at line 497 of file fx2regs.h.

#define bmIV1   bmBIT3

Definition at line 496 of file fx2regs.h.

#define bmIV2   bmBIT4

Definition at line 495 of file fx2regs.h.

#define bmIV3   bmBIT5

Definition at line 494 of file fx2regs.h.

#define bmIV4   bmBIT6

Definition at line 493 of file fx2regs.h.

#define bmLASTRD   bmBIT5

Definition at line 484 of file fx2regs.h.

#define bmNAKALL   bmBIT7

Definition at line 619 of file fx2regs.h.

#define bmNOAUTOARM   bmBIT1

Definition at line 615 of file fx2regs.h.

#define bmNOSYNSOF   bmBIT2

Definition at line 533 of file fx2regs.h.

#define bmNPAK   (bmBIT6 | bmBIT5 | bmBIT4)

Definition at line 550 of file fx2regs.h.

#define bmOEP   bmBIT5

Definition at line 607 of file fx2regs.h.

#define bmPRTCSTB   bmBIT5

Definition at line 450 of file fx2regs.h.

#define bmQUERYTOGGLE   bmBIT7

Definition at line 572 of file fx2regs.h.

#define bmRENUM   bmBIT1

Definition at line 534 of file fx2regs.h.

#define bmRESETTOGGLE   bmBIT5

Definition at line 574 of file fx2regs.h.

#define bmRXD0OUT   bmBIT3

Definition at line 476 of file fx2regs.h.

#define bmRXD1OUT   bmBIT4

Definition at line 475 of file fx2regs.h.

#define bmSDPAUTO   bmBIT0

Definition at line 570 of file fx2regs.h.

#define bmSETTOGGLE   bmBIT6

Definition at line 573 of file fx2regs.h.

#define bmSIGRESUME   bmBIT0

Definition at line 535 of file fx2regs.h.

#define bmSIZE   bmBIT3

Definition at line 565 of file fx2regs.h.

#define bmSKIPCOMMIT   bmBIT0

Definition at line 616 of file fx2regs.h.

#define bmSOF   bmBIT1

Definition at line 504 of file fx2regs.h.

#define bmSTART   bmBIT7

Definition at line 482 of file fx2regs.h.

#define bmSTOP   bmBIT6

Definition at line 483 of file fx2regs.h.

#define bmSTOPIE   bmBIT1

Definition at line 490 of file fx2regs.h.

#define bmSUDAV   bmBIT0

Definition at line 505 of file fx2regs.h.

#define bmSUSP   bmBIT3

Definition at line 502 of file fx2regs.h.

#define bmSUTOK   bmBIT2

Definition at line 503 of file fx2regs.h.

#define bmT0OUT   bmBIT0

Definition at line 479 of file fx2regs.h.

#define bmT1OUT   bmBIT1

Definition at line 478 of file fx2regs.h.

#define bmT2EX   bmBIT6

Definition at line 473 of file fx2regs.h.

#define bmT2OUT   bmBIT2

Definition at line 477 of file fx2regs.h.

#define bmTOGCTLEPMASK   bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0

Definition at line 575 of file fx2regs.h.

#define bmTYPE   (bmBIT4|bmBIT5)

Definition at line 566 of file fx2regs.h.

#define bmURES   bmBIT4

Definition at line 501 of file fx2regs.h.

#define bmVALID   bmBIT7

Definition at line 568 of file fx2regs.h.

#define bmWORDWIDE   bmBIT0

Definition at line 611 of file fx2regs.h.

#define bmWU   bmBIT6

Definition at line 538 of file fx2regs.h.

#define bmWU2   bmBIT7

Definition at line 537 of file fx2regs.h.

#define bmWU2EN   bmBIT1

Definition at line 542 of file fx2regs.h.

#define bmWU2POL   bmBIT5

Definition at line 539 of file fx2regs.h.

#define bmWUEN   bmBIT0

Definition at line 543 of file fx2regs.h.

#define bmWUPOL   bmBIT4

Definition at line 540 of file fx2regs.h.

#define bmZEROLENIN   bmBIT2

Definition at line 610 of file fx2regs.h.

#define EXTAUTODAT1   XAUTODAT1

Autoptr2 MOVX access.

Definition at line 131 of file fx2regs.h.

#define EXTAUTODAT2   XAUTODAT2

Definition at line 132 of file fx2regs.h.

#define INT4IN   bmBIT1

Definition at line 528 of file fx2regs.h.

---

Variable Documentation

sfr at _XPAGE

Definition at line 310 of file fx2regs.h.

sbit at AC

Definition at line 423 of file fx2regs.h.

sfr at ACC

Definition at line 431 of file fx2regs.h.

sfr at AUTOPTRH1

Definition at line 323 of file fx2regs.h.

sfr at AUTOPTRH2

Definition at line 325 of file fx2regs.h.

sfr at AUTOPTRL1

Definition at line 324 of file fx2regs.h.

sfr at AUTOPTRL2

Definition at line 326 of file fx2regs.h.

sfr at AUTOPTRSETUP

Definition at line 355 of file fx2regs.h.

sfr at B

Definition at line 439 of file fx2regs.h.

xdata at volatile BYTE BPADDRH

Breakpoint.

Definition at line 50 of file fx2regs.h.

xdata at volatile BYTE BPADDRL

Breakpoint Address H.

Definition at line 51 of file fx2regs.h.

xdata at volatile BYTE BREAKPT

Restore FIFOS to default state.

Definition at line 49 of file fx2regs.h.

sbit at C_T2

Definition at line 404 of file fx2regs.h.

sfr at CKCON

Definition at line 296 of file fx2regs.h.

xdata at volatile BYTE CLRERRCNT

USB Error counter and limit.

Definition at line 115 of file fx2regs.h.

sbit at CP_RL2

Definition at line 403 of file fx2regs.h.

xdata at volatile BYTE CPUCS

Definition at line 44 of file fx2regs.h.

sbit at CY

Definition at line 424 of file fx2regs.h.

sfr at DPH

Definition at line 276 of file fx2regs.h.

sfr at DPH1

Definition at line 278 of file fx2regs.h.

sfr at DPL

Definition at line 275 of file fx2regs.h.

sfr at DPL1

Definition at line 277 of file fx2regs.h.

sfr at DPS

Definition at line 279 of file fx2regs.h.

sbit at EA

Definition at line 350 of file fx2regs.h.

xdata at volatile BYTE ECC1B0

ECC Reset.

Definition at line 245 of file fx2regs.h.

xdata at volatile BYTE ECC1B1

ECC1 Byte 0.

Definition at line 246 of file fx2regs.h.

xdata at volatile BYTE ECC1B2

ECC1 Byte 1.

Definition at line 247 of file fx2regs.h.

xdata at volatile BYTE ECC2B0

ECC1 Byte 2.

Definition at line 248 of file fx2regs.h.

xdata at volatile BYTE ECC2B1

ECC2 Byte 0.

Definition at line 249 of file fx2regs.h.

xdata at volatile BYTE ECC2B2

ECC2 Byte 1.

Definition at line 250 of file fx2regs.h.

xdata at volatile BYTE ECCCFG

512 byte EP8 buffer (IN or OUT)

Definition at line 243 of file fx2regs.h.

xdata at volatile BYTE ECCRESET

ECC Configuration.

Definition at line 244 of file fx2regs.h.

sbit at EI2C

Definition at line 435 of file fx2regs.h.

sfr at EICON

Definition at line 425 of file fx2regs.h.

sfr at EIE

Definition at line 432 of file fx2regs.h.

sbit at EIEX4

Definition at line 436 of file fx2regs.h.

sbit at EIEX5

Definition at line 437 of file fx2regs.h.

sbit at EIEX6

Definition at line 438 of file fx2regs.h.

sfr at EIP

Definition at line 440 of file fx2regs.h.

sbit at EIPX4

Definition at line 444 of file fx2regs.h.

sbit at EIPX5

Definition at line 445 of file fx2regs.h.

sbit at EIPX6

Definition at line 446 of file fx2regs.h.

sfr at EP01STAT

Definition at line 383 of file fx2regs.h.

xdata at volatile BYTE EP0BCH

USB Function address.

Definition at line 147 of file fx2regs.h.

xdata at volatile BYTE EP0BCL

Endpoint 0 Byte Count H.

Definition at line 148 of file fx2regs.h.

xdata at volatile BYTE EP0BUF[64]

UDMA In only, host terminated use only.

Definition at line 233 of file fx2regs.h.

xdata at volatile BYTE EP0CS

Endpoint 8 Byte Count L.

Definition at line 159 of file fx2regs.h.

xdata at volatile BYTE EP1INBC

Endpoint 1 OUT Byte Count.

Definition at line 150 of file fx2regs.h.

xdata at volatile BYTE EP1INBUF[64]

EP1-OUT buffer.

Definition at line 235 of file fx2regs.h.

xdata at volatile BYTE EP1INCFG

Endpoint 1-OUT Configuration.

Definition at line 60 of file fx2regs.h.

xdata at volatile BYTE EP1INCS

Endpoint 1 OUT Control and Status.

Definition at line 161 of file fx2regs.h.

xdata at volatile BYTE EP1OUTBC

Endpoint 0 Byte Count L.

Definition at line 149 of file fx2regs.h.

xdata at volatile BYTE EP1OUTBUF[64]

EP0 IN-OUT buffer.

Definition at line 234 of file fx2regs.h.

xdata at volatile BYTE EP1OUTCFG

Chip Revision Control.

Definition at line 59 of file fx2regs.h.

xdata at volatile BYTE EP1OUTCS

Endpoint Control and Status.

Definition at line 160 of file fx2regs.h.

sfr at EP2468STAT

Definition at line 352 of file fx2regs.h.

sfr at EP24FIFOFLGS

Definition at line 353 of file fx2regs.h.

xdata at volatile BYTE EP2AUTOINLENH

Endpoint 8 FIFO configuration.

Definition at line 69 of file fx2regs.h.

xdata at volatile BYTE EP2AUTOINLENL

Endpoint 2 Packet Length H (IN only).

Definition at line 70 of file fx2regs.h.

xdata at volatile BYTE EP2BCH

Endpoint 1 IN Byte Count.

Definition at line 151 of file fx2regs.h.

xdata at volatile BYTE EP2BCL

Endpoint 2 Byte Count H.

Definition at line 152 of file fx2regs.h.

xdata at volatile BYTE EP2CFG

Endpoint 1-IN Configuration.

Definition at line 61 of file fx2regs.h.

xdata at volatile BYTE EP2CS

Endpoint 1 IN Control and Status.

Definition at line 162 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOBCH

Endpoint 8 Flags.

Definition at line 170 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOBCL

EP2 FIFO total byte count H.

Definition at line 171 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOBUF[1024]

EP1-IN buffer.

Definition at line 236 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOCFG

Endpoint 8 Configuration.

Definition at line 65 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOFLGS

Endpoint 8 Control and Status.

Definition at line 166 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOIE

Force OUT Packet End.

Definition at line 94 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOIRQ

Endpoint 2 Flag Interrupt Enable.

Definition at line 95 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOPFH

Endpoint 8 Packet Length L (IN only).

Definition at line 77 of file fx2regs.h.

xdata at volatile BYTE EP2FIFOPFL

EP2 Programmable Flag trigger H.

Definition at line 78 of file fx2regs.h.

xdata at volatile BYTE EP2GPIFFLGSEL

GPIF Transaction Count Byte 0.

Definition at line 197 of file fx2regs.h.

xdata at volatile BYTE EP2GPIFPFSTOP

EP2 GPIF Flag select.

Definition at line 198 of file fx2regs.h.

xdata at volatile BYTE EP2GPIFTRIG

Stop GPIF EP2 transaction on prog. flag.

Definition at line 199 of file fx2regs.h.

xdata at volatile BYTE EP2ISOINPKTS

EP8 Programmable Flag trigger L.

Definition at line 85 of file fx2regs.h.

xdata at volatile BYTE EP4AUTOINLENH

Endpoint 2 Packet Length L (IN only).

Definition at line 71 of file fx2regs.h.

xdata at volatile BYTE EP4AUTOINLENL

Endpoint 4 Packet Length H (IN only).

Definition at line 72 of file fx2regs.h.

xdata at volatile BYTE EP4BCH

Endpoint 2 Byte Count L.

Definition at line 153 of file fx2regs.h.

xdata at volatile BYTE EP4BCL

Endpoint 4 Byte Count H.

Definition at line 154 of file fx2regs.h.

xdata at volatile BYTE EP4CFG

Endpoint 2 Configuration.

Definition at line 62 of file fx2regs.h.

xdata at volatile BYTE EP4CS

Endpoint 2 Control and Status.

Definition at line 163 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOBCH

EP2 FIFO total byte count L.

Definition at line 172 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOBCL

EP4 FIFO total byte count H.

Definition at line 173 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOBUF[1024]

512/1024-byte EP2 buffer (IN or OUT)

Definition at line 237 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOCFG

Endpoint 2 FIFO configuration.

Definition at line 66 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOFLGS

Endpoint 2 Flags.

Definition at line 167 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOIE

Endpoint 2 Flag Interrupt Request.

Definition at line 96 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOIRQ

Endpoint 4 Flag Interrupt Enable.

Definition at line 97 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOPFH

EP2 Programmable Flag trigger L.

Definition at line 79 of file fx2regs.h.

xdata at volatile BYTE EP4FIFOPFL

EP4 Programmable Flag trigger H.

Definition at line 80 of file fx2regs.h.

xdata at volatile BYTE EP4GPIFFLGSEL

EP2 FIFO Trigger.

Definition at line 200 of file fx2regs.h.

xdata at volatile BYTE EP4GPIFPFSTOP

EP4 GPIF Flag select.

Definition at line 201 of file fx2regs.h.

xdata at volatile BYTE EP4GPIFTRIG

Stop GPIF EP4 transaction on prog. flag.

Definition at line 202 of file fx2regs.h.

xdata at volatile BYTE EP4ISOINPKTS

EP2 (if ISO) IN Packets per frame (1-3).

Definition at line 86 of file fx2regs.h.

sfr at EP68FIFOFLGS

Definition at line 354 of file fx2regs.h.

xdata at volatile BYTE EP6AUTOINLENH

Endpoint 4 Packet Length L (IN only).

Definition at line 73 of file fx2regs.h.

xdata at volatile BYTE EP6AUTOINLENL

Endpoint 6 Packet Length H (IN only).

Definition at line 74 of file fx2regs.h.

xdata at volatile BYTE EP6BCH

Endpoint 4 Byte Count L.

Definition at line 155 of file fx2regs.h.

xdata at volatile BYTE EP6BCL

Endpoint 6 Byte Count H.

Definition at line 156 of file fx2regs.h.

xdata at volatile BYTE EP6CFG

Endpoint 4 Configuration.

Definition at line 63 of file fx2regs.h.

xdata at volatile BYTE EP6CS

Endpoint 4 Control and Status.

Definition at line 164 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOBCH

EP4 FIFO total byte count L.

Definition at line 174 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOBCL

EP6 FIFO total byte count H.

Definition at line 175 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOBUF[1024]

512 byte EP4 buffer (IN or OUT)

Definition at line 238 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOCFG

Endpoint 4 FIFO configuration.

Definition at line 67 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOFLGS

Endpoint 4 Flags.

Definition at line 168 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOIE

Endpoint 4 Flag Interrupt Request.

Definition at line 98 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOIRQ

Endpoint 6 Flag Interrupt Enable.

Definition at line 99 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOPFH

EP4 Programmable Flag trigger L.

Definition at line 81 of file fx2regs.h.

xdata at volatile BYTE EP6FIFOPFL

EP6 Programmable Flag trigger H.

Definition at line 82 of file fx2regs.h.

xdata at volatile BYTE EP6GPIFFLGSEL

EP4 FIFO Trigger.

Definition at line 203 of file fx2regs.h.

xdata at volatile BYTE EP6GPIFPFSTOP

EP6 GPIF Flag select.

Definition at line 204 of file fx2regs.h.

xdata at volatile BYTE EP6GPIFTRIG

Stop GPIF EP6 transaction on prog. flag.

Definition at line 205 of file fx2regs.h.

xdata at volatile BYTE EP6ISOINPKTS

EP4 (if ISO) IN Packets per frame (1-3).

Definition at line 87 of file fx2regs.h.

xdata at volatile BYTE EP8AUTOINLENH

Endpoint 6 Packet Length L (IN only).

Definition at line 75 of file fx2regs.h.

xdata at volatile BYTE EP8AUTOINLENL

Endpoint 8 Packet Length H (IN only).

Definition at line 76 of file fx2regs.h.

xdata at volatile BYTE EP8BCH

Endpoint 6 Byte Count L.

Definition at line 157 of file fx2regs.h.

xdata at volatile BYTE EP8BCL

Endpoint 8 Byte Count H.

Definition at line 158 of file fx2regs.h.

xdata at volatile BYTE EP8CFG

Endpoint 6 Configuration.

Definition at line 64 of file fx2regs.h.

xdata at volatile BYTE EP8CS

Endpoint 6 Control and Status.

Definition at line 165 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOBCH

EP6 FIFO total byte count L.

Definition at line 176 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOBCL

EP8 FIFO total byte count H.

Definition at line 177 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOBUF[1024]

512/1024-byte EP6 buffer (IN or OUT)

Definition at line 239 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOCFG

Endpoint 6 FIFO configuration.

Definition at line 68 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOFLGS

Endpoint 6 Flags.

Definition at line 169 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOIE

Endpoint 6 Flag Interrupt Request.

Definition at line 100 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOIRQ

Endpoint 8 Flag Interrupt Enable.

Definition at line 101 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOPFH

EP6 Programmable Flag trigger L.

Definition at line 83 of file fx2regs.h.

xdata at volatile BYTE EP8FIFOPFL

EP8 Programmable Flag trigger H.

Definition at line 84 of file fx2regs.h.

xdata at volatile BYTE EP8GPIFFLGSEL

EP6 FIFO Trigger.

Definition at line 206 of file fx2regs.h.

xdata at volatile BYTE EP8GPIFPFSTOP

EP8 GPIF Flag select.

Definition at line 207 of file fx2regs.h.

xdata at volatile BYTE EP8GPIFTRIG

Stop GPIF EP8 transaction on prog. flag.

Definition at line 208 of file fx2regs.h.

xdata at volatile BYTE EP8ISOINPKTS

EP6 (if ISO) IN Packets per frame (1-3).

Definition at line 88 of file fx2regs.h.

xdata at volatile BYTE EPIE

USB Interrupt Requests.

Definition at line 108 of file fx2regs.h.

xdata at volatile BYTE EPIRQ

Endpoint Interrupt Enables.

Definition at line 109 of file fx2regs.h.

sbit at ERESI

Definition at line 429 of file fx2regs.h.

xdata at volatile BYTE ERRCNTLIM

USB Error Interrupt Requests.

Definition at line 114 of file fx2regs.h.

sbit at ES0

Definition at line 347 of file fx2regs.h.

sbit at ES1

Definition at line 349 of file fx2regs.h.

sbit at ET0

Definition at line 344 of file fx2regs.h.

sbit at ET1

Definition at line 346 of file fx2regs.h.

sbit at ET2

Definition at line 348 of file fx2regs.h.

sbit at EUSB

Definition at line 434 of file fx2regs.h.

sbit at EX0

Definition at line 343 of file fx2regs.h.

sbit at EX1

Definition at line 345 of file fx2regs.h.

sbit at EXEN2

Definition at line 406 of file fx2regs.h.

sbit at EXF2

Definition at line 409 of file fx2regs.h.

sfr at EXIF

Definition at line 307 of file fx2regs.h.

sbit at F0

Definition at line 422 of file fx2regs.h.

xdata at volatile BYTE FIFOPINPOLAR

230 Kbaud clock for T0,T1,T2

Definition at line 53 of file fx2regs.h.

xdata at volatile BYTE FIFORESET

FIFO FLAGC and FLAGD Assignments.

Definition at line 48 of file fx2regs.h.

sbit at FL

Definition at line 418 of file fx2regs.h.

xdata at volatile BYTE FLOWEQ0CTL

Defines flow/hold decision criteria.

Definition at line 220 of file fx2regs.h.

xdata at volatile BYTE FLOWEQ1CTL

CTL states during active flow state.

Definition at line 221 of file fx2regs.h.

xdata at volatile BYTE FLOWHOLDOFF

CTL states during hold flow state.

Definition at line 222 of file fx2regs.h.

xdata at volatile BYTE FLOWLOGIC

Defines GPIF flow state.

Definition at line 219 of file fx2regs.h.

xdata at volatile BYTE FLOWSTATE

Abort GPIF cycles.

Definition at line 218 of file fx2regs.h.

xdata at volatile BYTE FLOWSTB

Definition at line 223 of file fx2regs.h.

xdata at volatile BYTE FLOWSTBEDGE

CTL/RDY Signal to use as master data strobe.

Definition at line 224 of file fx2regs.h.

xdata at volatile BYTE FLOWSTBHPERIOD

Defines active master strobe edge.

Definition at line 225 of file fx2regs.h.

xdata at volatile BYTE FNADDR

Microframe count, 0-7.

Definition at line 143 of file fx2regs.h.

xdata at volatile BYTE GPCR2

ECC2 Byte 2.

Definition at line 253 of file fx2regs.h.

xdata at volatile BYTE GPIF_WAVE_DATA

Definition at line 39 of file fx2regs.h.

xdata at volatile BYTE GPIFABORT

RDY pin states.

Definition at line 214 of file fx2regs.h.

xdata at volatile BYTE GPIFADRH

CTL OUT pin drive.

Definition at line 189 of file fx2regs.h.

xdata at volatile BYTE GPIFADRL

GPIF Address H.

Definition at line 190 of file fx2regs.h.

xdata at volatile BYTE GPIFCTLCFG

Inactive Bus, CTL states.

Definition at line 188 of file fx2regs.h.

xdata at volatile BYTE GPIFHOLDAMOUNT

Half Period of output master strobe.

Definition at line 226 of file fx2regs.h.

xdata at volatile BYTE GPIFIDLECS

Waveform Selector.

Definition at line 186 of file fx2regs.h.

xdata at volatile BYTE GPIFIDLECTL

GPIF Done, GPIF IDLE drive mode.

Definition at line 187 of file fx2regs.h.

xdata at volatile BYTE GPIFIE

Endpoint Interrupt Requests.

Definition at line 110 of file fx2regs.h.

xdata at volatile BYTE GPIFIRQ

GPIF Interrupt Enable.

Definition at line 111 of file fx2regs.h.

xdata at volatile BYTE GPIFREADYCFG

Read GPIF Data L, no transac trigger.

Definition at line 212 of file fx2regs.h.

xdata at volatile BYTE GPIFREADYSTAT

Internal RDY,Sync/Async, RDY5CFG.

Definition at line 213 of file fx2regs.h.

sfr at GPIFSGLDATH

Definition at line 386 of file fx2regs.h.

sfr at GPIFSGLDATLNOX

Definition at line 388 of file fx2regs.h.

sfr at GPIFSGLDATLX

Definition at line 387 of file fx2regs.h.

xdata at volatile BYTE GPIFTCB0

GPIF Transaction Count Byte 1.

Definition at line 195 of file fx2regs.h.

xdata at volatile BYTE GPIFTCB1

GPIF Transaction Count Byte 2.

Definition at line 194 of file fx2regs.h.

xdata at volatile BYTE GPIFTCB2

GPIF Transaction Count Byte 3.

Definition at line 193 of file fx2regs.h.

xdata at volatile BYTE GPIFTCB3

GPIF Address L.

Definition at line 192 of file fx2regs.h.

sfr at GPIFTRIG

Definition at line 384 of file fx2regs.h.

xdata at volatile BYTE GPIFWFSELECT

8 bytes of SETUP data

Definition at line 185 of file fx2regs.h.

xdata at volatile BYTE I2CS

I/O PORTE Alternate Configuration.

Definition at line 125 of file fx2regs.h.

xdata at volatile BYTE I2CTL

Data.

Definition at line 127 of file fx2regs.h.

xdata at volatile BYTE I2DAT

Control & Status.

Definition at line 126 of file fx2regs.h.

xdata at volatile BYTE IBNIE

Endpoint 8 Flag Interrupt Request.

Definition at line 102 of file fx2regs.h.

xdata at volatile BYTE IBNIRQ

IN-BULK-NAK Interrupt Enable.

Definition at line 103 of file fx2regs.h.

sfr at IE

Definition at line 341 of file fx2regs.h.

sbit at IE0

Definition at line 284 of file fx2regs.h.

sbit at IE1

Definition at line 286 of file fx2regs.h.

xdata at volatile BYTE IFCONFIG

Control & Status.

Definition at line 45 of file fx2regs.h.

xdata at volatile BYTE INPKTEND

EP8 (if ISO) IN Packets per frame (1-3).

Definition at line 89 of file fx2regs.h.

sfr at INT2CLR

Definition at line 338 of file fx2regs.h.

xdata at volatile BYTE INT2IVEC

Clear Error Counter EC[3..0].

Definition at line 116 of file fx2regs.h.

sfr at INT4CLR

Definition at line 339 of file fx2regs.h.

xdata at volatile BYTE INT4IVEC

Interupt 2 (USB) Autovector.

Definition at line 117 of file fx2regs.h.

sbit at INT6

Definition at line 427 of file fx2regs.h.

xdata at volatile BYTE INTSETUP

Interupt 4 (FIFOS & GPIF) Autovector.

Definition at line 118 of file fx2regs.h.

sfr at IOA

Chip Features.

SFRs below According to TRM 15.2, only rows 0 and 8 of the SFRs are bit addressible row 0: IOA, IOB, IOC, IOD, SCON1, PSW, ACC, B row 8: TCON, SCON0, IE, IP, T2CON, IECON, EIE, EIP

All others have to move a byte to the SRF address

Definition at line 264 of file fx2regs.h.

sfr at IOB

Definition at line 297 of file fx2regs.h.

sfr at IOC

Definition at line 328 of file fx2regs.h.

sfr at IOD

Definition at line 356 of file fx2regs.h.

sfr at IOE

Definition at line 366 of file fx2regs.h.

sfr at IP

Definition at line 373 of file fx2regs.h.

sbit at IT0

Definition at line 283 of file fx2regs.h.

sbit at IT1

Definition at line 285 of file fx2regs.h.

xdata at volatile BYTE MICROFRAME

USB Frame count L.

Definition at line 142 of file fx2regs.h.

xdata at volatile BYTE NAKIE

IN-BULK-NAK interrupt Request.

Definition at line 104 of file fx2regs.h.

xdata at volatile BYTE NAKIRQ

Endpoint Ping NAK interrupt Enable.

Definition at line 105 of file fx2regs.h.

sfr at OEA

Definition at line 367 of file fx2regs.h.

sfr at OEB

Definition at line 368 of file fx2regs.h.

sfr at OEC

Definition at line 369 of file fx2regs.h.

sfr at OED

Definition at line 370 of file fx2regs.h.

sfr at OEE

Definition at line 371 of file fx2regs.h.

xdata at volatile BYTE OUTPKTEND

Force IN Packet End.

Definition at line 90 of file fx2regs.h.

sbit at OV

Definition at line 419 of file fx2regs.h.

sbit at P

Definition at line 417 of file fx2regs.h.

sbit at PA0

Definition at line 266 of file fx2regs.h.

sbit at PA1

Definition at line 267 of file fx2regs.h.

sbit at PA2

Definition at line 268 of file fx2regs.h.

sbit at PA3

Definition at line 269 of file fx2regs.h.

sbit at PA4

Definition at line 270 of file fx2regs.h.

sbit at PA5

Definition at line 271 of file fx2regs.h.

sbit at PA6

Definition at line 272 of file fx2regs.h.

sbit at PA7

Definition at line 273 of file fx2regs.h.

sbit at PB0

Definition at line 299 of file fx2regs.h.

sbit at PB1

Definition at line 300 of file fx2regs.h.

sbit at PB2

Definition at line 301 of file fx2regs.h.

sbit at PB3

Definition at line 302 of file fx2regs.h.

sbit at PB4

Definition at line 303 of file fx2regs.h.

sbit at PB5

Definition at line 304 of file fx2regs.h.

sbit at PB6

Definition at line 305 of file fx2regs.h.

sbit at PB7

Definition at line 306 of file fx2regs.h.

sbit at PC0

Definition at line 330 of file fx2regs.h.

sbit at PC1

Definition at line 331 of file fx2regs.h.

sbit at PC2

Definition at line 332 of file fx2regs.h.

sbit at PC3

Definition at line 333 of file fx2regs.h.

sbit at PC4

Definition at line 334 of file fx2regs.h.

sbit at PC5

Definition at line 335 of file fx2regs.h.

sbit at PC6

Definition at line 336 of file fx2regs.h.

sbit at PC7

Definition at line 337 of file fx2regs.h.

sfr at PCON

Definition at line 280 of file fx2regs.h.

sbit at PD0

Definition at line 358 of file fx2regs.h.

sbit at PD1

Definition at line 359 of file fx2regs.h.

sbit at PD2

Definition at line 360 of file fx2regs.h.

sbit at PD3

Definition at line 361 of file fx2regs.h.

sbit at PD4

Definition at line 362 of file fx2regs.h.

sbit at PD5

Definition at line 363 of file fx2regs.h.

sbit at PD6

Definition at line 364 of file fx2regs.h.

sbit at PD7

Definition at line 365 of file fx2regs.h.

sbit at PI2C

Definition at line 443 of file fx2regs.h.

xdata at volatile BYTE PINFLAGSAB

Interface Configuration.

Definition at line 46 of file fx2regs.h.

xdata at volatile BYTE PINFLAGSCD

FIFO FLAGA and FLAGB Assignments.

Definition at line 47 of file fx2regs.h.

xdata at volatile BYTE PORTACFG

Interrupt 2&4 Setup.

Definition at line 122 of file fx2regs.h.

xdata at volatile BYTE PORTCCFG

I/O PORTA Alternate Configuration.

Definition at line 123 of file fx2regs.h.

xdata at volatile BYTE PORTECFG

I/O PORTC Alternate Configuration.

Definition at line 124 of file fx2regs.h.

sbit at PS0

Definition at line 379 of file fx2regs.h.

sbit at PS1

Definition at line 381 of file fx2regs.h.

sfr at PSW

Definition at line 415 of file fx2regs.h.

sbit at PT0

Definition at line 376 of file fx2regs.h.

sbit at PT1

Definition at line 378 of file fx2regs.h.

sbit at PT2

Definition at line 380 of file fx2regs.h.

sbit at PUSB

Definition at line 442 of file fx2regs.h.

sbit at PX0

Definition at line 375 of file fx2regs.h.

sbit at PX1

Definition at line 377 of file fx2regs.h.

sbit at RB8

Definition at line 315 of file fx2regs.h.

sbit at RB81

Definition at line 394 of file fx2regs.h.

sfr at RCAP2H

Definition at line 412 of file fx2regs.h.

sfr at RCAP2L

Definition at line 411 of file fx2regs.h.

sbit at RCLK

Definition at line 408 of file fx2regs.h.

sbit at REN

Definition at line 317 of file fx2regs.h.

sbit at REN1

Definition at line 396 of file fx2regs.h.

xdata at volatile BYTE RES_WAVEDATA_END

Definition at line 40 of file fx2regs.h.

sbit at RESI

Definition at line 428 of file fx2regs.h.

xdata at volatile BYTE REVCTL

Chip Revision.

Definition at line 55 of file fx2regs.h.

xdata at volatile BYTE REVID

FIFO polarities.

Definition at line 54 of file fx2regs.h.

sbit at RI

Definition at line 313 of file fx2regs.h.

sbit at RI1

Definition at line 392 of file fx2regs.h.

sbit at RS0

Definition at line 420 of file fx2regs.h.

sbit at RS1

Definition at line 421 of file fx2regs.h.

sfr at SBUF0

Definition at line 321 of file fx2regs.h.

sfr at SBUF1

Definition at line 400 of file fx2regs.h.

sfr at SCON0

Definition at line 311 of file fx2regs.h.

sfr at SCON1

Definition at line 390 of file fx2regs.h.

xdata at volatile BYTE SETUPDAT[8]

Setup Data Pointer Auto Mode.

Definition at line 181 of file fx2regs.h.

sbit at SM0

Definition at line 320 of file fx2regs.h.

sbit at SM01

Definition at line 399 of file fx2regs.h.

sbit at SM1

Definition at line 319 of file fx2regs.h.

sbit at SM11

Definition at line 398 of file fx2regs.h.

sbit at SM2

Definition at line 318 of file fx2regs.h.

sbit at SM21

Definition at line 397 of file fx2regs.h.

sbit at SMOD1

Definition at line 430 of file fx2regs.h.

sfr at SP

Definition at line 274 of file fx2regs.h.

xdata at volatile BYTE SUDPTRCTL

Setup Data Pointer low address byte.

Definition at line 180 of file fx2regs.h.

xdata at volatile BYTE SUDPTRH

EP8 FIFO total byte count L.

Definition at line 178 of file fx2regs.h.

xdata at volatile BYTE SUDPTRL

Setup Data Pointer high address byte.

Definition at line 179 of file fx2regs.h.

xdata at volatile BYTE SUSPEND

USB Control & Status.

Definition at line 137 of file fx2regs.h.

sfr at T2CON

Definition at line 401 of file fx2regs.h.

sbit at TB8

Definition at line 316 of file fx2regs.h.

sbit at TB81

Definition at line 395 of file fx2regs.h.

sbit at TCLK

Definition at line 407 of file fx2regs.h.

sfr at TCON

Definition at line 281 of file fx2regs.h.

sbit at TF0

Definition at line 288 of file fx2regs.h.

sbit at TF1

Definition at line 290 of file fx2regs.h.

sbit at TF2

Definition at line 410 of file fx2regs.h.

sfr at TH0

Definition at line 294 of file fx2regs.h.

sfr at TH1

Definition at line 295 of file fx2regs.h.

sfr at TH2

Definition at line 414 of file fx2regs.h.

sbit at TI

Definition at line 314 of file fx2regs.h.

sbit at TI1

Definition at line 393 of file fx2regs.h.

sfr at TL0

Definition at line 292 of file fx2regs.h.

sfr at TL1

Definition at line 293 of file fx2regs.h.

sfr at TL2

Definition at line 413 of file fx2regs.h.

sfr at TMOD

Definition at line 291 of file fx2regs.h.

xdata at volatile BYTE TOGCTL

Wakeup source and polarity.

Definition at line 139 of file fx2regs.h.

sbit at TR0

Definition at line 287 of file fx2regs.h.

sbit at TR1

Definition at line 289 of file fx2regs.h.

sbit at TR2

Definition at line 405 of file fx2regs.h.

xdata at volatile BYTE UART230

Breakpoint Address L.

Definition at line 52 of file fx2regs.h.

xdata at volatile BYTE UDMACRCH

Data delay shift.

Definition at line 227 of file fx2regs.h.

xdata at volatile BYTE UDMACRCL

CRC Upper byte.

Definition at line 228 of file fx2regs.h.

xdata at volatile BYTE UDMACRCQUAL

CRC Lower byte.

Definition at line 229 of file fx2regs.h.

xdata at volatile BYTE USBCS

Definition at line 136 of file fx2regs.h.

xdata at volatile BYTE USBERRIE

GPIF Interrupt Request.

Definition at line 112 of file fx2regs.h.

xdata at volatile BYTE USBERRIRQ

USB Error Interrupt Enables.

Definition at line 113 of file fx2regs.h.

xdata at volatile BYTE USBFRAMEH

Toggle Control.

Definition at line 140 of file fx2regs.h.

xdata at volatile BYTE USBFRAMEL

USB Frame count H.

Definition at line 141 of file fx2regs.h.

xdata at volatile BYTE USBIE

Endpoint Ping NAK interrupt Request.

Definition at line 106 of file fx2regs.h.

xdata at volatile BYTE USBIRQ

USB Int Enables.

Definition at line 107 of file fx2regs.h.

xdata at volatile BYTE WAKEUPCS

Put chip into suspend.

Definition at line 138 of file fx2regs.h.

xdata at volatile BYTE XAUTODAT1

I2C Control.

Definition at line 128 of file fx2regs.h.

xdata at volatile BYTE XAUTODAT2

Autoptr1 MOVX access.

Definition at line 129 of file fx2regs.h.

xdata at volatile BYTE XGPIFSGLDATH

EP8 FIFO Trigger.

Definition at line 209 of file fx2regs.h.

xdata at volatile BYTE XGPIFSGLDATLNOX

Read/Write GPIF Data L & trigger transac.

Definition at line 211 of file fx2regs.h.

xdata at volatile BYTE XGPIFSGLDATLX

GPIF Data H (16-bit mode only).

Definition at line 210 of file fx2regs.h.